d a t a sh eet product speci?cation file under integrated circuits, ic06 september 1993 integrated circuits 74hc/hct154 4-to-16 line decoder/demultiplexer for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
september 1993 2 philips semiconductors product speci?cation 4-to-16 line decoder/demultiplexer 74hc/hct154 features 16-line demultiplexing capability decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs 2-input enable gate for strobing or expansion output capability: standard i cc category: msi general description the 74hc/hct154 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct154 decoders accept four active high binary address inputs and provide 16 mutually exclusive active low outputs. the 2-input enable gate can be used to strobe the decoder to eliminate the normal decoding glitches on the outputs, or it can be used for the expansion of the decoder. the enable gate has two anded inputs which must be low to enable the outputs. the 154 can be used as a 1-to-16 demultiplexer by using one of the enable inputs as the multiplexed data input. when the other enable is low, the addressed output will follow the state of the applied data. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl/ t plh propagation delay a n , e n to y n c l = 15 pf; v cc =5 v 11 13 ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 60 60 pf
september 1993 3 philips semiconductors product speci?cation 4-to-16 line decoder/demultiplexer 74hc/hct154 pin description pin no. symbol name and function 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17 y 0 to y 15 outputs (active low) 18, 19 e 0 , e 1 enable inputs (active low) 12 gnd ground (0 v) 23, 22, 21, 20 a 0 to a 3 address inputs 24 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol. (a) (b) fig.4 functional diagram.
september 1993 4 philips semiconductors product speci?cation 4-to-16 line decoder/demultiplexer 74hc/hct154 function table note 1. h = high voltage level l = low voltage level x = dont care inputs outputs e 0 e 1 a 0 a 1 a 2 a 3 y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 10 y 11 y 12 y 13 y 14 y 15 h h l h l h x x x x x x x x x x x x h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h l l l l l l l l l h l h l l h h l l l l l l l l l h h h h l h h h h l h h h h l h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h l l l l l l l l l h l h l l h h h h h h l l l l h h h h h h h h h h h h h h h h l h h h h l h h h h l h h h h l h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h l l l l l l l l l h l h l l h h l l l l h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h l h h h h l h h h h l h h h h l h h h h h h h h h h h h h h h h l l l l l l l l l h l h l l h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h l h h h h l h h h h l h h h h l fig.5 logic diagram.
september 1993 5 philips semiconductors product speci?cation 4-to-16 line decoder/demultiplexer 74hc/hct154 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay a n to y n 36 13 10 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.6 t phl / t plh propagation delay e n to y n 39 14 11 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.7 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 figs 6 and 7
september 1993 6 philips semiconductors product speci?cation 4-to-16 line decoder/demultiplexer 74hc/hct154 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf input unit load coefficient a n e n 1.0 1.0 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay a n to y n 16 35 44 53 ns 4.5 fig.6 t phl / t plh propagation delay e n to y n 15 32 40 48 ns 4.5 fig.7 t thl / t tlh output transition time 7 15 19 22 ns 4.5 figs 6 and 7
september 1993 7 philips semiconductors product speci?cation 4-to-16 line decoder/demultiplexer 74hc/hct154 ac waveforms fig.6 waveforms showing the address input (a n ) to output ( y n ) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.7 waveforms showing the enable input ( en) to output ( y n ) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. application information fig.8 1-of-16 decoder; low level output is selected. package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.9 1-of-16 demultiplexer; logic level on selected outputs follow the logic level on the data input.
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